Conventional nonvolatile memory devices include mask read-only memories (ROMs), electrically erasable programmable read-only memories (EEPROMs), and flash EEPROMs. These conventional nonvolatile memory devices typically include memory cells that can store one of two information states, e.g., an "ON" state and an "OFF" state. In order to store N-bits of data, N single-bit memory cells are typically used.
Many conventional transistor-type one-bit memory cells define logical states using the threshold voltage of a transistor, e.g., the state of data stored in a transistor may be distinguished by the level of the threshold voltage of the transistor. In a typical mask ROM, for example, threshold voltage for a cell transistor is controlled by injection of ions using ion implantation techniques. In typical EPROMs, EEPROMs and flash EEPROMs, threshold voltage for a cell transistor is controlled by controlling the amount of charge stored in a floating gate of the transistor.
Threshold voltage control can be used to implement a transistor memory cell that is capable of representing multiple bits of information. For example, as illustrated in FIG. 1, cell transistors of a mask ROM may be programmed with logical values "00", "01", "10" or "11", by setting their threshold levels at a value falling within one of four ranges around nominal threshold voltages Vth1, Vth2, Vth3, Vth4.
To determine the logical state of such a multi level cell, a series of different word line voltages are applied to the cell, as illustrated in FIG. 2. In particular, a word line connected to memory cell is driven at a first word line voltage V.sub.WL1 while determining the presence or absence of a current through the memory cell at a first sensing point using, for example, a sense amplifier circuit. The word line is then driven at a second word line voltage V.sub.WL2 higher than the first word line voltage V.sub.WL1, and the presence or absence of current through the memory cell is determined at a second sensing point. Finally, a third word line voltage V.sub.WL3 higher than the first and second word line voltages V.sub.WL1 and V.sub.WL2 is applied to the word line, and the presence or absence of a current flowing through the cell is determined at a third sensing point. As illustrated in FIG. 3, the order in which the word line voltages are applied can be varied. An example of such a data reading operation is described in U.S. Pat. No. 5,457,650 to Sugiura et al.
Outputs from a sense amplifier of a multi-level memory typically are logically combined by an output circuit to produce a multi-bit output. To maintain small chip size, this output circuit desirably has a low number of components.